1. Field of the Invention
The present invention relates to data processing systems, and more particularly to an improved instruction translator unit for decoding macroinstructions and for generating microinstructions necessary for an execution unit to emulate the function encoded in the macroinstruction.
2. Description of the Prior Art
In U.S. Pat. No. 4,325,120 Stephen R. Colley et al entitled "Data Processing System" granted on Mar. 13, 1982, is disclosed an object-oriented data processor architecture which takes full advantage of recent advances in the state-of-the-art of very large-scale, integrated circuit technology. The patent application describes a general-purpose processor which is able to perform generalized computation over a wide spectrum of data types supported by the architecture. Such a complex microprocessor requires a number of complex logical circuits. With present-day integrated-circuit technology, this complex microprocessor is too large to be fabricated on a single chip and therefore it must be partitioned and fabricated on a number of chips. Several factors must be considered in determining where to partition this logic. One must consider the distribution of heat dissipation over the chips and balance this dissipation as uniformly as possible. Furthermore, effective communication between chips should be handled with a minimum amount of interconnections. Finally, there should be a clean flow of information with a minimum amount of chip-to-chip feedback to complete a particular flow. This is because transferring data back-and-fourth across chip boundaries requires time, power, and buffering. Therefore, an optimum partitioning minimizes the number of cycles necessary to perform a function. As described in the above-identified Colley, et al patent, the microprocessor is partitioned between two chips with an instruction unit on one chip and an execution unit on another chip. Communication between chips is performed over an interchip bus. Off-chip communication with external devices, such as input/output devices, is accomplished over an interface more fully described in U.S. Pat. No. 4,315,308 entitled "Microprocessor Interface between a Microprocessor Chip and Peripheral Subsystems, " by Daniel K. Jackson, Ser. No. 972,007, filed on Dec. 21, 1978.
The following is a summary of some of the prior approaches to the problem of partitioning a microprocessor among a number of integrated circuit chips.
In Hoff, Jr. et al U.S. Pat. No. 3,821,715 a microprocessor is partitioned at the memory interface and is fabricated on several chips. Each memory subsystem includes decoding circuitry to determine which of the plurality of memory chips is being addressed by the central processing unit. This patent represents those types of systems wherein memories are fabricated on separate chips and are coupled to a common data bus and coupled to the CPU. The present invention is concerned with partitioning the microprocessor at the instruction unit, execution unit interface.
The Walker U.S. Pat. No. 3,918,030 discloses a microprocessor which is partitioned at the instruction unit decoder for the replication of functions. A number of instruction decoders are provided, each comprising a separate package which responds to one--and only one--instruction. The present invention relates to a different approach in which the instruction decoder within the instruction unit receives all instructions and decodes them accordingly, thereby implementing a pipelined architecture.
U.S. Pat. No. 3,984,813 discloses a microprocessor that is partitioned between two chips, with the memory on one chip, and the CPU on another chip. The CPU chip incorporates all of the standard elements of a CPU, but does not contain a program counter. The dedicated program counter, on another chip, is driven in synchronism with the operation of the CPU so that appropriate control signals are transmitted from the CPU to control the program counter. The patent does not disclose how to optimize the partitioning of a CPU which is too large to fit on one chip, such as that described above with reference to the Colley, et al patent application.
Finally, the Cockerill, et al U.S. Pat. No. 4,057,846 discloses a pipelined microprocessor; howeer, it does not teach one how to utilize pipelining techniques to partition a microprocessor between two chips.
It is a primary object of the present invention to provide an instruction unit for receiving macroinstructions and for generating a series of microinstructions for utilization by an execution unit which is fabricated on a separate chip.
It is a further obect of the present invention to provide an instruction unit which is capable of generating microinstruction sequences for one macroinstruction, while decoding and interpreting the fields of a next macroinstruction.
It is also an object of this invention to provide an instruction unit which processes variable-bit-length instructions.
A further object of the invention is to provide an instruction unit which provides a clean flow of microinstructions to an external execution unit with a minimum amount of feedback from said execution unit to complete a particular flow.